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L3G4200D
MEMS motion sensor: three-axis digital output gyroscope
Features

Three selectable full scales (250/500/2000 dps) I2C/SPI digital output interface 16 bit rate value data output Two digital output lines (interrupt and dataready) Integrated low and high pass filters with user selectable bandwidth Embedded self-test Wide supply voltage, 2.4 V to 3.6 V Low voltage compatible IOs, 1.8 V Embedded power-down and sleep mode High shock survivability Extended operating temperature range (-40 C to +85 C) ECOPACK(R) RoHS and "Green" compliant (see Section 6)
LGA-16 (4x4x1 mm)
Description
The L3G4200D is a low-power three-axis gyroscope providing three different user selectable full scales (250/500/2000 dps). It includes a sensing element and an IC interface able to provide the detected angular rate to the external world through a digital interface (I2C/SPI). The sensing element is manufactured using specialized micromachining processes, while the IC interface is realized using a CMOS technology that allows designing a dedicated circuit which is trimmed to better match the sensing element characteristics. The L3G4200D is available in a plastic land grid array (LGA) package and provides excellent temperature stability and high resolution over an extend operating temperature range (-40 C to +85 C).
Applications

Gaming and virtual reality input devices Motion control with MMI (man-machine interface) GPS navigation systems Appliances and robotics
Table 1.
Device summary
Temperature range (C) -40 to + 85 Package LGA-16 (4x4x1) Tape and reel Packing Tray
Order code L3G4200D L3G4200DTR
February 2010
Doc ID 17116 Rev 1
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Contents
L3G4200D
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.1 2.3.2 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.1 3.1.2 3.1.3 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Zero-rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2
Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
Digital main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 5.2 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2.1 5.2.2 5.2.3 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Filter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Mechanical characteristics @ Vdd = 3.0 V, T = 25 C unless otherwise noted . . . . . . . . . . 8 Electrical characteristics @ Vdd =3.0 V, T=25 C unless otherwise noted. . . . . . . . . . . . . . 9 SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 I2C terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Transfer when Master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Transfer when Master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Transfer when Master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 17 Transfer when Master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 17 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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List of figures
L3G4200D
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 L3G4200D external low-pass filter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SPI slave timing diagram (2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C slave timing diagram (3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Multiple bytes SPI read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Multiple bytes SPI write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SPI read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 LGA-16: mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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Block diagram and pin description
1
Block diagram and pin description
Figure 1. Block diagram
+
x,y,z
X+ Y+ Z+ M U X
CHARGE AMP
MIXER
LOW-PASS FILTER A D C
ZYX-
D I G I T A L
F I L T E R I N G
I2C SPI
CS SCL/SPC SDA/SDO/SDI SDO
DRIVING MASS
Feedback loop
REFERENCE
TRIMMING CIRCUITS
CLOCK & PHASE GENERATOR
CONTROL LOGIC & INTERRUPT GEN.
INT DRDY
AM06080v1
The vibration of the structure is maintained by a drive circuitry in a feedback loop.The sensing signal is filtered and appears as digital signal at the output.
1.1
Pin description
Figure 2. Pin connection
PLLFILT
+
1
Z
GND
RES
Vdd
X
+
13
16 1
Y
RES RES RES
12
Vdd_IO SCL/SPC SDA/SDI/SDO
BOTTOM VIEW
9 8 5 4
+
(TOP VIEW) DIRECTIONS OF THE DETECTABLE ANGULAR RATES
X
RES
SDO/SA0
RES
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INT
DRDY
CS
AM06081v1
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Block diagram and pin description
L3G4200D
Table 2.
Pin# 1 2
Pin description
Name Vdd_IO SCL SPC SDA SDI SDO SDO SA0 CS DRDY INT Reserved Reserved Reserved Reserved Reserved GND PLLFILT Reserved Vdd Power supply for I/O pins I2C serial clock (SCL) SPI serial port clock (SPC) I2C serial data (SDA) SPI serial data input (SDI) 3-wire interface serial data output (SDO) SPI serial data output (SDO) I2C less significant bit of the device address (SA0) SPI enable I2C/SPI mode selection (1: I2C mode; 0: SPI enabled) Data ready Programmable Interrupt Connect to GND Connect to GND Connect to GND Connect to GND Connect to GND 0 V supply Phase Locked Loop Filter (see Figure_3) Connect to Vdd Power supply Function
3
4 5 6 7 8 9 10 11 12 13 14 15 16
Figure 3.
L3G4200D external low-pass filter values(a)
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Block diagram and pin description
Table 3.
Filter values
Component C1 R2 C2 Typical values 10 nF 10 k 470 pF
a. Pin 14 PLLFILT maximum voltage level is equal to Vdd.
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Mechanical and electrical specifications
L3G4200D
2
2.1
Table 4.
Symbol
Mechanical and electrical specifications
Mechanical characteristics
Mechanical characteristics @ Vdd = 3.0 V, T = 25 C unless otherwise noted(1)
Parameter Test condition Min. Typ.(2) 250 FS Angular rate range User selectable 500 2000 FS = 250 dps So Sensitivity FS = 500 dps FS = 2000 dps SoDr Sensitivity change vs. temperature From -40 C to +85 C FS = 250 dps DVoff Digital zero-rate level FS = 500 dps FS = 2000 dps OffDr NL Zero-rate level change vs temperature Non linearity(3) FS = 250 dps FS = 2000 dps Best fit straight line FS = 250 dps DST Self-test output change FS = 500 dps FS = 2000 dps Rn ODR Top Rate noise density Digital output data rate Operating temperature range -40 BW = 40 Hz 8.75 17.50 70 2 10 15 75 0.03 0.04 0.2 130 200 530 0.03 100/200/ 400/800 +85 dps/vHz Hz C dps dps/C dps/C % FS dps % mdps/digit dps Max. Unit
1. The product is factory calibrated at 3.0 V. The operational power supply range is specified in Table 5. 2. Typical specifications are not guaranteed. 3. Guaranteed by design.
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Mechanical and electrical specifications
2.2
Table 5.
Symbol Vdd Vdd_IO Idd IddSL IddPdn Top
Electrical characteristics
Electrical characteristics @ Vdd =3.0 V, T=25 C unless otherwise noted(1)
Parameter Supply voltage I/O pins supply voltage Supply current Supply current in sleep mode(4) Supply current in power-down mode Operating temperature range
(3)
Test condition
Min. 2.4 1.71
Typ.(2) 3.0
Max. 3.6 Vdd+0.1
Unit V V mA mA A
6.1 1.5 Selectable by digital interface 5 -40 +85
C
1. The product is factory calibrated at 3.0V. 2. Typical specifications are not guaranteed. 3. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the reading chain is powered off. 4. Sleep mode allows to reduce turn on time compared to Power down.
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Mechanical and electrical specifications
L3G4200D
2.3
2.3.1
Communication interface characteristics
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 6.
SPI slave timing values
Value(1) Parameter Min. Max. ns 10 5 8 5 15 50 6 50 ns MHz SPI clock cycle SPI clock frequency CS setup time CS hold time SDI input setup time SDI input hold time SDO valid output time SDO output hold time SDO output disable time 100 Unit
Symbol tc(SPC) fc(SPC) tsu(CS) th(CS) tsu(SI) th(SI) tv(SO) th(SO) tdis(SO)
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production.
Figure 4.
SPI slave timing diagram (2)
2. Measurement points are done at 0.2*Vdd_IO and 0.8*Vdd_IO, for both Input and Output port
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Mechanical and electrical specifications
2.3.2
I2C - Inter IC control interface
Subject to general operating conditions for Vdd and Top.
Table 7.
Symbol f(SCL) tw(SCLL) tw(SCLH) tsu(SDA) th(SDA)
I2C slave timing values
I2C Standard mode(1) Parameter Min SCL clock frequency SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time START condition hold time Repeated START condition setup time STOP condition setup time Bus free time between STOP and START condition 4 4.7 4 4.7 0 4.7 4.0 250 0 3.45 1000 300 Max 100 Min 0 1.3 s 0.6 100 0 20 + 0.1Cb (2) 20 + 0.1Cb (2) 0.6 0.6 s 0.6 1.3 0.9 300 ns 300 ns s Max 400 kHz I2C Fast mode (1) Unit
tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(ST) tsu(SR) tsu(SP) tw(SP:SR)
1. Data based on standard I2C protocol requirement, not tested in production. 2. Cb = total capacitance of one bus line, in pF.
Figure 5.
I2C slave timing diagram (3)
REPEATED START
START
t su(SR)
SDA
t w(SP:SR)
START
t f(SDA)
t r(SDA)
t su(SDA)
t h(SDA)
t su(SP)
STOP
SCL
t h(ST)
t w(SCLL)
t w(SCLH)
t r(SCL)
t f(SCL)
3
Measurement points are done at 0.2*Vdd_IO and 0.8*Vdd_IO, for both ports
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Absolute maximum ratings
L3G4200D
3
Absolute maximum ratings
Stresses above those listed as "Absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 8.
Symbol Vdd TSTG Sg ESD Supply voltage Storage temperature range Acceleration g for 0.1 ms Electrostatic discharge protection
Absolute maximum ratings
Ratings Maximum value -0.3 to 4.8 -40 to +125 10,000 2 (HBM) Unit V C g kV
This is a mechanical shock sensitive device, improper handling can cause permanent damage to the part This is an ESD sensitive device, improper handling can cause permanent damage to the part
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Absolute maximum ratings
3.1
3.1.1
Terminology
Sensitivity
An angular rate gyroscope is device that produces a positive-going digital output for counterclockwise rotation around the sensible axis considered. Sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. This value changes very little over temperature and time.
3.1.2
Zero-rate level
Zero-rate level describes the actual output signal if there is no angular rate present. Zerorate level of precise MEMS sensors is, to some extent, a result of stress to the sensor and therefore zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. This value changes very little over temperature and time.
3.1.3
Self-test
Self-test allows to test the mechanical and electric part of the sensor, allowing the seismic mass to be moved by means of an electrostatic test-force. When the ST is activated by IC, an actuation force is applied to the sensor, emulating a definite Coriolis force. In this case the sensor output will exhibit an output change.
3.2
Soldering information
The LGA package is compliant with the ECOPACK(R), RoHS and "Green" standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020. Leave "Pin 1 Indicator" unconnected during soldering. Land pattern and soldering recommendations are available at www.st.com/mems.
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Digital main blocks
L3G4200D
4
4.1
Digital main blocks
Block diagram
Figure 6. Block diagram
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Digital interfaces
5
Digital interfaces
The registers embedded inside the L3G4200D may be accessed through both the I2C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are mapped onto the same pins. To select/exploit the I2C interface, CS line must be tied high (i.e connected to Vdd_IO). Table 9. Serial interface pin description
Pin description SPI enable I2C/SPI mode selection (1: I2C mode; 0: SPI enabled) I2C Serial Clock (SCL) SPI Serial Port Clock (SPC) I2C Serial Data (SDA) SPI Serial Data Input (SDI) 3-wire Interface Serial Data Output (SDO) SPI Serial Data Output (SDO) I2C less significant bit of the device address
Pin name CS SCL/SPC
SDA/SDI/SDO
SDO
5.1
I2C serial interface
The L3G4200D I2C is a bus slave. The I2C is employed to write data into registers whose content can also be read back. The relevant I2C terminology is given in the table below. Table 10.
Term Transmitter Receiver Master Slave
I2C terminology
Description The device which sends data to the bus The device which receives data from the bus The device which initiates a transfer, generates clock signals and terminates a transfer The device addressed by the master
There are two signals associated with the I2C bus: the Serial Clock Line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines must be connected to Vdd_IO through external pull-up resistor. When the bus is free both the lines are high. The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as with the normal mode.
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Digital interfaces
L3G4200D
5.1.1
I2C operation
The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the Master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the Master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the Master. The Slave ADdress (SAD) associated to the L3G4200D is 110100xb. SDO pin can be used to modify less significant bit of the device address. If SDO pin is connected to voltage supply LSb is `1' (address 1101001b) else if SDO pin is connected to ground LSb value is `0' (address 1101000b). This solution permits to connect and address two different gyroscopes to the same I2C bus. Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. The I2C embedded inside the L3G4200D behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, a 8-bit sub-address will be transmitted: the 7 LSb represent the actual register address while the MSB enables address auto increment. If the MSb of the SUB field is 1, the SUB (register address) will be automatically incremented to allow multiple data read/write. The slave address is completed with a Read/Write bit. If the bit was `1' (Read), a repeated START (SR) condition will have to be issued after the two sub-address bytes; if the bit is `0' (Write) the Master will transmit to the slave with direction unchanged. Table 11 explains how the SAD+Read/Write bit pattern is composed, listing all the possible configurations. Table 11. SAD+Read/Write patterns
SAD[6:1] 110100 110100 110100 110100 SAD[0] = SDO 0 0 1 1 R/W 1 0 1 0 SAD+R/W 11010001 (D1h) 11010000 (D0h) 11010011 (D3h) 11010010 (D2h)
Command Read Write Read Write
Table 12.
Master Slave
Transfer when Master is writing one byte to slave
ST SAD + W SAK SUB SAK DATA SAK SP
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Digital interfaces
Table 13.
Master Slave
Transfer when Master is writing multiple bytes to slave
ST SAD + W SAK SUB SAK DATA SAK DATA SAK SP
Table 14.
Master Slave ST
Transfer when Master is receiving (reading) one byte of data from slave
SAD + W SAK SUB SAK SR SAD + R SAK DATA NMAK SP
Table 15.
Slave
Transfer when Master is receiving (reading) multiple bytes of data from slave
SUB SAK SAK SR SAD+R SAK DATA MAK DATA MAK DATA NMAK SP
Master ST SAD+W
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit (MSb) first. If a receiver can't receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn't acknowledge the slave address (i.e. it is not able to receive because it is performing some real time function) the data line must be left HIGH by the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition. In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the address of first register to be read. In the presented communication format MAK is Master Acknowledge and NMAK is No Master Acknowledge.
5.2
SPI bus interface
The SPI is a bus slave. The SPI allows to write and read the registers of the device. The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.
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Digital interfaces Figure 7.
CS SPC SDI
RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
L3G4200D Read and write protocol
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CS is the Serial Port Enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the Serial Port Clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are respectively the Serial Port Data Input and Output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC. Both the Read Register and Write Register commands are completed in 16 clock pulses or in multiple of 8 in case of multiple bytes read/write. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS. bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SDO at the start of bit 8. bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands. When 1, the address will be auto incremented in multiple read/write commands. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that will be written into the device (MSb first). bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). In multiple read/write commands further blocks of 8 clock periods will be added. When MS bit is 0 the address used to read/write data remains the same for every block. When MS bit is 1 the address used to read/write data is incremented at every block. The function and the behavior of SDI and SDO remain unchanged.
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Digital interfaces
5.2.1
SPI read
Figure 8. SPI read protocol
CS SPC SDI
RW MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI Read command is performed with 16 clock pulses. Multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). bit 16-... : data DO(...-8). Further data in multiple byte reading. Figure 9.
CS SPC SDI
RW MS AD5 AD4 AD3 AD2 AD1 AD0
Multiple bytes SPI read protocol (2 bytes example)
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8
5.2.2
SPI write
Figure 10. SPI write protocol
CS SPC SDI
RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
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Digital interfaces
L3G4200D
The SPI Write command is performed with 16 clock pulses. Multiple byte write command is performed adding blocks of 8 clock pulses at the previous one. bit 0: WRITE bit. The value is 0. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple writing. bit 2 -7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that will be written inside the device (MSb first). bit 16-... : data DI(...-8). Further data in multiple byte writing. Figure 11. Multiple bytes SPI write protocol (2 bytes example)
CS SPC SDI
RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
5.2.3
SPI read in 3-wires mode
3-wires mode is entered by setting to 1 bit SIM (SPI serial interface mode selection) in CTRL_REG2. Figure 12. SPI read protocol in 3-wires mode
CS SPC SDI/O
RW MS AD5 AD4 AD3 AD2 AD1 AD0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI Read command is performed with 16 clock pulses: bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). Multiple read command is also available in 3-wires mode.
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Package information
6
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
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Package information Figure 13. LGA-16: mechanical data and package dimensions
L3G4200D
Dimensions Ref.
A1 A2 A3 d D1 E1 L2 M N1 N2 P1 P2 T1 T2 k 3.850 3.850 0.855 0.200 0.300 4.000 4.000 1.950 0.100 0.650 0.975 1.750 1.525 0.400 0.300 0.050 4.150 4.150
mm Min. Typ. Max.
1.100
Outline and mechanical data
LGA-16 (4x4x1 mm) Land Grid Array Package
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Revision history
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Revision history
Table 16.
Date 11-Feb-2010
Document revision history
Revision 1 First release. Changes
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